Effect of ESD Layout on the Assembly Yield and Reliability

Author

Lee, Yung-Huei ; Chowdhury, Das ; Dimagiba, Richard ; Ciccariello, Robert

Author_Institution

Intel Corp., Santa Clara, CA

fYear

2006

fDate

11-13 Dec. 2006

Firstpage

1

Lastpage

4

Abstract

The paper investigated the thin film stress effect on the wire-bond assembly yield and reliability. ESD layouts that utilize the bond pad area increase the thermomechanical stress of the thin-films in the pad area and affect the assembly. Experimental data on products with different metal layout designs are compared to characterize the assembly yield and reliability performance. A computer finite element mechanical stress analysis is also conducted to quantify the interaction of pad design with the assembly. Experimental data and simulation showed a good correlation between the metal layout and the assembly yield and reliability. A degradation model is proposed with the support of detail failure analysis. A robust design solution is suggested to reduce the mechanical stress and improve the assembly yield and reliability

Keywords

electrostatic discharge; failure analysis; finite element analysis; integrated circuit layout; integrated circuit reliability; integrated circuit yield; thermal stresses; thin films; electrostatic discharge; failure analysis; finite element analysis; integrated circuit layout; integrated circuit reliability; integrated circuit yield; robust design; thermomechanical stress; thin film stress effect; wire-bond assembly yield; Assembly; Bonding; Computational modeling; Degradation; Electrostatic discharge; Finite element methods; Thermal stresses; Thermomechanical processes; Thin films; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2006. IEDM '06. International

Conference_Location

San Francisco, CA

Print_ISBN

1-4244-0439-8

Electronic_ISBN

1-4244-0439-8

Type

conf

DOI

10.1109/IEDM.2006.346970

Filename

4154405