DocumentCode
2391178
Title
High performance Hybrid and Monolithic Backside Thinned CMOS Imagers realized using a new integration process
Author
Munck, Koen De ; Tezcan, Deniz Sabuncuoglu ; Borgers, Tom ; Ruythooren, Wouter ; Moor, Piet De ; Sedky, Sherif ; Toccafondi, Cinzia ; Bogaerts, Jan ; Hoof, Chris Van
Author_Institution
IMEC, Leuven
fYear
2006
fDate
11-13 Dec. 2006
Firstpage
1
Lastpage
4
Abstract
Hybrid and monolithic thinned backside illuminated CMOS imagers operating at full depletion at low substrate voltages were developed. The combination of a 50 mum EPI layer with varying doping concentration and trenches to reduce crosstalk is unique. All thin wafer processing is performed on 200 mm wafers using a specially developed temporary carrier process. As a result, working imagers exhibiting high pixel yield, high quantum efficiency and low dark current are demonstrated
Keywords
CMOS image sensors; epitaxial layers; 200 mm; 50 micron; CMOS image sensor; dark current; doping concentration; monolithic thinned backside; quantum efficiency; thin wafer processing; CMOS image sensors; CMOS process; Crosstalk; Dark current; Detectors; Doping; Glass; Low voltage; Pixel; Sensor arrays;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2006. IEDM '06. International
Conference_Location
San Francisco, CA
Print_ISBN
1-4244-0438-X
Electronic_ISBN
1-4244-0439-8
Type
conf
DOI
10.1109/IEDM.2006.346979
Filename
4154414
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