Instruction based testbench architecture

Author

Choi, Ho-Seok ; Lee, Seung-Beom ; Park, Sin-Chong

Author_Institution

Inf. & Commun. Univ., Taejon, South Korea

fYear

2005

fDate

20-24 July 2005

Firstpage

329

Lastpage

333

Abstract

This paper presents the synthesizable testbench architecture based on the defined instruction for standalone mode verification. The proposed testbench performs fast emulation with low resource and increases flexibility and reusability with variable description of instructions. To prove the performance of our testbench, we verified IEEE 802.11a PHY baseband system and compare with co-sim mode and modified co-sim mode emulation.

Keywords

circuit simulation; formal verification; hardware-software codesign; integrated circuit testing; IEEE 802.11a PHY baseband system; fast emulation; instruction based testbench architecture; modified co-sim mode emulation; standalone mode verification; synthesizable testbench architecture; Baseband; Circuit simulation; Emulation; Hardware; Life estimation; Performance evaluation; Physical layer; Signal processing; Software testing; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on

Print_ISBN

0-7695-2403-6

Type

conf

DOI

10.1109/IWSOC.2005.76

Filename

1530966

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2391271