Electrical packaging requirements of CMOS ULSI devices, and fundamental electrical performance limits of single chip packages

Due to low cost manufacturing and a well established infrastructure for large volume off-shore assembly, Single Chip Packages (SCPs) continue to be the work-horse packages for a wide range of present and future CMOS ULSI devices. To understand the overall collective chip-package electrical limits, one should first understand in detail the electrical requirements of the device that is going to be housed in that package. In this work a detailed methodology is developed to calculate the CMOS devices´ electrical packaging requirements. Several closed-form equations are derived for present and future CMOS ULSI devices. Both the speed constrained and current sink/source constrained drivers are considered. Based on these closed form equations,the electrical packaging requirements of CMOS ULSI devices can be generated