A 80-Gbit/s D-type flip-flop circuit using InP HEMT technology

Author

Suzuki, T. ; Takahashi, T. ; Hirose, T. ; Takigawa, M.

Author_Institution

Fujitsu Labs. Ltd., Atsugi, Japan

fYear

2003

fDate

9-12 Nov. 2003

Firstpage

165

Lastpage

168

Abstract

80 Gbit/s operation of a static D-type flip-flop (D-FF) circuit was achieved using InP-based HEMT technology with a cut-off frequency of 245 GHz and a transconductance of 1500 mS/mm. To generate 80 GHz differential clock signals from the single phase one in the circuit, a rat-race circuit was placed in front of the clock buffer. The power supply voltage was -5.7 V and power consumption was 1.2 W. Its performance was measured using a selector module that we developed. The results showed that the D-FF operated at 80 Gbit/s, which was more than half as much again as speeds reported to date.

Keywords

HEMT integrated circuits; III-V semiconductors; buffer circuits; flip-flops; indium compounds; -5.7 V; 1.2 W; 1500 mS/mm; 245 GHz; 80 GHz; 80 Gbit/s; D-FF; HEMT technology; InP; clock buffer rat-race circuit; differential clock signals; static D-type flip-flop circuit; Circuits; Clocks; Cutoff frequency; Flip-flops; HEMTs; Indium phosphide; Power supplies; Signal generators; Transconductance; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 2003. 25th Annual Technical Digest 2003. IEEE

Conference_Location

San Diego, CA, USA

ISSN

1064-7775

Print_ISBN

0-7803-7833-4

Type

conf

DOI

10.1109/GAAS.2003.1252386

Filename

1252386