Placement of logic schematics and topological via minimization

Traditionally placement and via minimization are considered separately, with via minimization following placement. We integrate the two problems, and propose a new objective function for the placement of logic schematics, i.e. topological via minimization. We use a graph theoretic approach and present an algorithm of time complexity O(kn³) for arbitrary schematics, here k is the fan-in/fan-out of the schematic. For a schematic consisting of a union of zero or more C_n, P_r and K_p,q we present an optimal algorithm of time complexity O(n) for sparse schematics and O(n₃ ) for dense schematics