Surface Potential Based poly-Si Thin-Film Transistor Model for SPICE

Author

Ikeda, Hiroyuki

Author_Institution

Mobile Display Bus. Group, Sony Corp., Kanagawa

fYear

2006

fDate

11-13 Dec. 2006

Firstpage

1

Lastpage

4

Abstract

This paper presents a surface potential based poly-Si thin-film transistor (SPT) model for SPICE which is formulated with both surface and grain boundary (GB) potentials calculated by Poisson equations. The drain current model includes GB induced mobility modulation, hot carrier effect, gate induced drain leakage, and trap dependent thermal leakage. The capacitance model is derived from physically partitioned charges. The SPT model has succeeded in simulating device performances with good accuracy

Keywords

Poisson equation; SPICE; grain boundaries; semiconductor device models; surface potential; thin film transistors; Poisson equation; SPICE; capacitance model; drain current model; gate induced drain leakage; grain boundary potentials; hot carrier effect; mobility modulation; poly-Si thin-film transistor model; surface potential; trap dependent thermal leakage; Capacitance; Circuit simulation; Crystallization; Displays; Grain boundaries; Hot carrier effects; Poisson equations; SPICE; Thin film transistors; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2006. IEDM '06. International

Conference_Location

San Francisco, CA

Print_ISBN

1-4244-0439-8

Electronic_ISBN

1-4244-0439-8

Type

conf

DOI

10.1109/IEDM.2006.346992

Filename

4154427