Title :
Design of a 64-bit, 100 MIPS microprocessor core IC for hybrid CMOS-SEED technology
Author :
Kiamilev, F.E. ; Lambirth, J.S. ; Rozier, R.G. ; Krishnamoorthy, A.V.
Author_Institution :
North Carolina Univ., Charlotte, NC, USA
Abstract :
We describe the design of a hybrid CMOS-SEED 64-bit microprocessor core IC with 192 optical I/Os. This 3.5 mm2 IC was fabricated and electrically tested at 100 MHz with a performance of 100 million 64-bit instructions per second (MIPS). The processor design includes a 64-bit arithmetic-logic unit (ALU) which implements 16 logic and 32 fixed-point arithmetic functions. A 1 cm2 chip can integrate thirty two 64-bit processors and achieve 3,200 64-bit MIPS. Further performance improvements can be achieved using improved processor architecture and/or a more advanced CMOS process. When combined with an appropriate photonic page buffer IC operating as a cache memory, it becomes possible to build a compact, two-chip parallel processor system
Keywords :
CMOS integrated circuits; SEEDs; digital arithmetic; microprocessor chips; optical logic; parallel architectures; 100 MHz; 32 fixed-point arithmetic functions; 64-bit arithmetic-logic unit; 64-bit instructions; MIPS microprocessor core IC; advanced CMOS process; cache memory; compact two-chip parallel processor system; electrically tested; free space optical interconnections; hybrid CMOS-SEED 64-bit microprocessor core IC; hybrid CMOS-SEED technology; optical computing; parallel architecture; performance improvements; photonic page buffer IC; processor architecture; CMOS integrated circuits; CMOS logic circuits; Hybrid integrated circuits; Integrated circuit testing; Logic design; Microprocessors; Optical buffering; Optical design; Photonic integrated circuits; Process design;
Conference_Titel :
Massively Parallel Processing Using Optical Interconnections, 1996., Proceedings of the Third International Conference on
Conference_Location :
Maui, HI
Print_ISBN :
0-8186-7591-8
DOI :
10.1109/MPPOI.1996.559038
