A novel design of a 6-GHz 8 × 8-b pipelined multiplier

This paper presents a design of 8-bit × 8-bit unsigned multiplier for high-speed digital signal processing (DSP) applications. High-speed is achieved by a new architecture implementing our earlier multiplication technique based in A. Khatibzadeh et a. (2005) in conventional register pipelining at the bit level. The multiplier is designed employing 0.18-μm CMOS process. HSPICE simulation results indicate that the proposed design performs multiplication rates up to 6 GHz under the supply voltage of 1.8V or 3.3 GHz under 1.4 V with about 25% times less power consumption. The comparison with Baugh-Wooley multiplier with same topology of the common elements shows that our multiplier consumes only 63% of the power of Baugh-Wooley multiplier with 40% reduction in latency.