DocumentCode
2391608
Title
Improving NoC Performance by Non-contention Ejection Architecture
Author
Lin, Shijun ; Shi, Jianghong
Author_Institution
Dept. of Commun. Eng., Xiamen Univ., Xiamen, China
fYear
2010
fDate
18-20 Aug. 2010
Firstpage
555
Lastpage
558
Abstract
In this paper, we propose a non-contention ejection architecture to improve the performance of Network-on-Chip (NoC). In this architecture, the contention is avoided by allocating a dedicated channel for every packet which may be ejected simultaneously, which make sure that packets in the network can be ejected promptly, and thus the number of packets stayed in the network is decreased and the communication performance is improved. Results show that compared with traditional ejection architecture, the proposed architecture improves the communication performance greatly with reasonable area increase.
Keywords
computer architecture; network-on-chip; NoC performance; network packet; network-on-chip architecture; noncontention ejection architecture; Computer architecture; IP networks; Nickel; Synchronization; System-on-a-chip; Throughput; Wire; Network-on-Chip; System-on-Chip; ejection architecture;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer and Information Science (ICIS), 2010 IEEE/ACIS 9th International Conference on
Conference_Location
Yamagata
Print_ISBN
978-1-4244-8198-9
Type
conf
DOI
10.1109/ICIS.2010.23
Filename
5590390
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