An FPGA design of a unified hash engine for IPSec authentication

Author

Khan, Esam ; El-Kharashi, M. Watheq ; Gebali, Fayez ; Abd-El-Barr, Mostafa

Author_Institution

Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada

fYear

2005

fDate

20-24 July 2005

Firstpage

450

Lastpage

453

Abstract

Hash functions are important security primitives used for authentication and data integrity. Among the most popular hash functions are MD5, SHA-1, and RIPEMD-160 that are used in conjunction with HMAC for IPSec. These three hash functions are based on an older one, MD4. Therefore, they have some similarities that can be exploited for designing a unified engine to perform the three hash functions. A unified engine design proves useful since the three algorithms are to be used by same implementation on the same core for authentication and data integrity using HMAC for IPSec. In this work, we design a SoC with a unified hash engine that can be reconfigured at runtime to perform one of the three hash functions. The results of our work show that the proposed engine has a balance between area and throughput compared to previous works.

Keywords

cryptography; data integrity; field programmable gate arrays; logic design; message authentication; FPGA design; HMAC; IPSec authentication; MD5; RIPEMD-160; SHA-1; data integrity; field programmable gate arrays; hash functions; unified hash engine; Algorithm design and analysis; Authentication; Computer security; Cryptography; Data security; Electrostatic precipitators; Engines; Field programmable gate arrays; Runtime; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on

Print_ISBN

0-7695-2403-6

Type

conf

DOI

10.1109/IWSOC.2005.41

Filename

1530989