Title :
A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control
Author :
Yang, Hao-I ; Yang, Shih-Chi ; Hsia, Mao-Chih ; Lin, Yung-Wei ; Lin, Yi-Wei ; Chen, Chien-Hen ; Chang, Chi-Shin ; Lin, Geng-Cing ; Chen, Yin-Nien ; Chuang, Ching-Te ; Hwang, Wei ; Jou, Shyh-Jye ; Lien, Nan-Chun ; Li, Hung-Yu ; Lee, Kuen-Di ; Shih, Wei-Chi
Author_Institution :
Dept. of Electron. Eng. & Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
Abstract :
This paper describes a high-performance low VMIN SRAM with a disturb-free 8 T cell. The SRAM utilizes single-ended buffer Read, and cross-point data-aware Write Word-Line structure with adaptive VVSS control to eliminate Read disturb and Half-Select disturb, thus facilitating bit-interleaving architecture and achieving low VMIN. A 512 Kb test chip is implemented in UMC 55 nm Standard Performance (SP) CMOS technology. The measurement results demonstrate operating frequency of 943 MHz at 1.2 V VDD and 209 MHz at 0.6 V VDD.
Keywords :
CMOS memory circuits; random-access storage; adaptive VVSS control; bit-interleaving architecture; cross-point data-aware write word-line structure; disturb-free 8T SRAM; disturb-free 8T cell; half-select disturb; high-performance low VMIN SRAM; single-ended buffer read; size 55 nm; standard performance CMOS technology; storage capacity 512 Kbit; CMOS integrated circuits; Computer architecture; Frequency measurement; Microprocessors; Random access memory; Semiconductor device measurement; Transistors;
Conference_Titel :
SOC Conference (SOCC), 2011 IEEE International
Conference_Location :
Taipei
Print_ISBN :
978-1-4577-1616-4
Electronic_ISBN :
2164-1676
DOI :
10.1109/SOCC.2011.6085080
