• DocumentCode
    239245
  • Title

    Optimization of combinational logic circuits through decomposition of truth table and evolution of sub-circuits

  • Author

    Manfrini, Francisco ; Barbosa, Helio J. C. ; Bernardino, Heder S.

  • Author_Institution
    Fed. Inst. of Sci. & Technol. of the Southeast of Minas Gerais, Fed. Univ. of Juiz de Fora, Juiz de Fora, Brazil
  • fYear
    2014
  • fDate
    6-11 July 2014
  • Firstpage
    945
  • Lastpage
    950
  • Abstract
    In this work, a genetic algorithm was used to design combinational logic circuits (CLCs), with the goal of minimizing the number of logic elements in the circuit. A new coding for circuits is proposed using a multiplexer (MUX) at the output of the circuit. This MUX divides the truth table into two distinct parts, with the evolution occurring in three sub-circuits connected to the control input and the two data inputs of the MUX. The methodology presented was tested with some benchmark circuits. The results were compared with those obtained using traditional design methods, as well as the results found in other articles, which used different heuristics to design CLCs.
  • Keywords
    benchmark testing; circuit optimisation; combinational circuits; genetic algorithms; logic design; logic testing; multiplexing equipment; CLC design; MUX; benchmark circuits; combinational logic circuit design; combinational logic circuit optimization; control input; genetic algorithm; logic elements; multiplexer; subcircuit evolution; truth table decomposition; Algorithm design and analysis; Benchmark testing; Encoding; Genetic algorithms; Heuristic algorithms; Input variables; Logic gates;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Evolutionary Computation (CEC), 2014 IEEE Congress on
  • Conference_Location
    Beijing
  • Print_ISBN
    978-1-4799-6626-4
  • Type

    conf

  • DOI
    10.1109/CEC.2014.6900565
  • Filename
    6900565