Title :
Buffer stage for fast response LDO
Author_Institution :
Catalyst Semicond. Romania, Bucharest, Romania
fDate :
28 Sept.-2 Oct. 2003
Abstract :
The paper presents a buffer stage used in a fast response LDO processed in a double-metal 0.8 μm CMOS process. The stage consists of a transconductance amplifier (OTA) in a unity-gain configuration. The buffer has a wideband architecture and is designed to drive the parasitic gate-to-source capacitance of the power transistor. Output impedance is lower than 2kΩ and current consumption is less than 20μA.
Keywords :
CMOS integrated circuits; voltage regulators; 0.8 micron; 2 kohm; 20 muA; buffer stage; current consumption; double-metal 0.8 μm CMOS process; fast response LDO; low dropout voltage regulators; output impedance; parasitic gate-to-source capacitance; power transistor; transconductance amplifier; unity-gain configuration; wideband architecture; CMOS process; CMOS technology; Impedance; Low voltage; MOS devices; MOSFETs; Power transistors; Threshold voltage; Transconductance; Wideband;
Conference_Titel :
Semiconductor Conference, 2003. CAS 2003. International
Print_ISBN :
0-7803-7821-0
DOI :
10.1109/SMICND.2003.1252453
