• DocumentCode
    2392925
  • Title

    Compiler-assisted technique for rapid performance estimation of FPGA-based processors

  • Author

    Aung, Yan Lin ; Lam, Siew-Kei ; Srikanthan, Thambipillai

  • Author_Institution
    Centre for High Performance Embedded Syst., Nanyang Technol. Univ., Singapore, Singapore
  • fYear
    2011
  • fDate
    26-28 Sept. 2011
  • Firstpage
    341
  • Lastpage
    346
  • Abstract
    This paper proposes a compiler-assisted technique to rapidly estimate performance of a wide range of FPGA processors without requiring actual execution on target processor or ISS. Experimental results show that this technique estimates performance of a widely-used FPGA processor with an average error of 2% in the order of seconds.
  • Keywords
    field programmable gate arrays; performance evaluation; program compilers; FPGA based processors; compiler assisted technique; rapid performance estimation; Assembly; Clocks; Estimation; Field programmable gate arrays; Finite impulse response filter; Hardware; Program processors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOC Conference (SOCC), 2011 IEEE International
  • Conference_Location
    Taipei
  • ISSN
    2164-1676
  • Print_ISBN
    978-1-4577-1616-4
  • Electronic_ISBN
    2164-1676
  • Type

    conf

  • DOI
    10.1109/SOCC.2011.6085116
  • Filename
    6085116
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2392925