DocumentCode :
2393037
Title :
Enhancing SAT-based equivalence checking with static logic implications
Author :
Arora, Rajat ; Hsiao, Michael S.
Author_Institution :
Virginia Tech, Blacksburg, VA, USA
fYear :
2003
fDate :
12-14 Nov. 2003
Firstpage :
63
Lastpage :
68
Abstract :
We propose a novel technique to improve SAT-based Combinational Equivalence Checking (CEC) by statically adding meaningful clauses to the CNF formula of the miter circuit. A fast preprocessing quickly builds up the implication graph for the miter circuit under verification, resulting in a large set of direct, indirect and extended backward implications. The non-trivial implications are converted into two-literal clauses and added to the miter CNF database. These added clauses constrain the search space, and provide correlation among the different variables, which enhances the Boolean Constraint Propagation (BCP). Experimental results on ISCAS´85 CEC instances show that with the added clauses, an average speedup of more than 950x was achieved.
Keywords :
Boolean functions; benchmark testing; combinational circuits; computability; constraint handling; equivalence classes; high level synthesis; Boolean constraint propagation; Boolean satisfiability; SAT-based equivalence checking; combinational equivalence checking; conjunctive normal form; extended backward implications; fast preprocessing; implementation algorithm; implication graph; miter-circuit under verification; static logic implications; Automatic test pattern generation; Boolean functions; Business continuity; Combinational circuits; Data structures; Databases; Electronic design automation and methodology; Input variables; Logic; Signal processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High-Level Design Validation and Test Workshop, 2003. Eighth IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-8236-6
Type :
conf
DOI :
10.1109/HLDVT.2003.1252476
Filename :
1252476
Link To Document :
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