DocumentCode
2393101
Title
Power characteristics of Asynchronous Networks-on-Chip
Author
Rashed, Maher ; Abd El Ghany, Mohamed A. ; Ismail, Mohammed
Author_Institution
Commun. Eng. Dept., German Univ. in Cairo, Cairo, Egypt
fYear
2011
fDate
26-28 Sept. 2011
Firstpage
160
Lastpage
165
Abstract
Power characteristics of different Asynchronous Network on Chip (NoC) architectures are developed. Among different NoC architectures, the Butterfly Fat Tree (BFT) dissipates the minimum power. With increasing the number of IP blocks, the relative power consumption of the interconnects and the associate repeaters of the Asynchronous NoC architecture decreases as compared to the power consumption of the network switches. The power dissipation of the Asynchronous architecture is decreased by up to 57% as compared to the power dissipation of the conventional Synchronous architecture. The BFT is more efficient with increasing the number of IP blocks.
Keywords
network-on-chip; asynchronous NoC architecture; asynchronous network-on-chip architecture; butterfly fat tree; network switches; power characteristics; power consumption; Computer architecture; IP networks; Power dissipation; Repeaters; Synchronization; Topology; Wires; GALS; Interswitch Links; NoC; Power Dissipation;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference (SOCC), 2011 IEEE International
Conference_Location
Taipei
ISSN
2164-1676
Print_ISBN
978-1-4577-1616-4
Electronic_ISBN
2164-1676
Type
conf
DOI
10.1109/SOCC.2011.6085125
Filename
6085125
Link To Document