• DocumentCode
    2393268
  • Title

    High-level test generation for hardware testing and software validation

  • Author

    Goloubeva, O. ; Reorda, M. Sonza ; Violante, M.

  • Author_Institution
    Politecnico di Torino, Italy
  • fYear
    2003
  • fDate
    12-14 Nov. 2003
  • Firstpage
    143
  • Lastpage
    148
  • Abstract
    It is now common for design teams to develop systems where hardware and software components cooperate; they are thus facing the challenging task of validating and testing systems where hardware and software parts exist. In this paper a high-level test generation approach is presented, which is able to produce input stimuli that can be fruitfully exploited for test and validation purposes of both hardware and software components. Experimental results are reported showing that the proposed approach produces high quality vectors in terms of the adopted metrics for hardware and software faults.
  • Keywords
    automatic test pattern generation; fault simulation; hardware-software codesign; system-on-chip; adopted metrics; behavioral system descriptions; hardware faults; hardware testing; high quality vectors; high-level fault models; high-level test generation; input stimuli; software faults; software validation; system-level design; system-on-chip; Automatic testing; Genetic mutations; Hardware; Manufacturing; Software testing; Software tools; Specification languages; System testing; System-level design; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Level Design Validation and Test Workshop, 2003. Eighth IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Print_ISBN
    0-7803-8236-6
  • Type

    conf

  • DOI
    10.1109/HLDVT.2003.1252488
  • Filename
    1252488