Title :
Impact of switch architectures on the performance of multistage interconnection networks
Author :
Zhou, Bin ; Atiquzzaman, M.
Author_Institution :
Dept. of Comput. Sci. & Eng., La Trobe Univ., Bundoora, Vic., Australia
Abstract :
Switching elements in interconnection networks for highly parallel shared memory computer systems may be implemented with different internal buffer structures. A multistage interconnection network (MIN) consist of several stages of small crossbar switching elements (SEs). The aim of this paper is to study the performance of a multibuffered MIN with different SEs architecture, in the presence of uniform and nonuniform traffic. For the purpose of comparison, the throughput and the network delay have been used as the performance measures
Keywords :
multistage interconnection networks; parallel architectures; performance evaluation; shared memory systems; crossbar switching elements; highly parallel shared memory computer systems; internal buffer structures; multibuffered MIN; multistage interconnection networks; network delay; nonuniform traffic; performance measures; switch architectures; throughput; uniform traffic; Computer architecture; Computer science; Hardware; Multiprocessing systems; Multiprocessor interconnection networks; Performance analysis; Queueing analysis; Switches; Throughput; Traffic control;
Conference_Titel :
TENCON '94. IEEE Region 10's Ninth Annual International Conference. Theme: Frontiers of Computer Technology. Proceedings of 1994
Print_ISBN :
0-7803-1862-5
DOI :
10.1109/TENCON.1994.369277
