Design considerations of phase-locked loop systems for spread spectrum clock generation compatibility

A technique was proposed which reduces the radiated emissions of a digital clock signal and its associated harmonics by as much as 10-20 dB, depending on frequency. This technique, referred to as spread spectrum clock generation (SSCG), reduces the radiated emissions associated with a clock signal by modulating the signal with a unique waveform. This technique can be used with minimal consideration when used in a system that does not utilize frequency dependent devices such as a phase-locked loop (PLL). For those designs which incorporate a PLL, attention must be given to the design of the PLL in order to minimize clock skew while at the same time maintain maximum attenuation of emissions. This paper presents design considerations and modeling techniques that an EMC engineer should consider when implementing SSCG in PLL based systems