Static Dual Edge Flip Flop Implementations on the 90nm Process

Dual edge triggered flip flops has twice the throughput, so they can be run at half the frequency to reduce power consumption at the clock distribution network. Three Dual edge flips were compared with each other. C-DDR-FF has the lowest power consumption due to its very simple structure, Ep-dsff has the lowest area due to the sharing of the clock pulse generator, while CBS-FF has the fastest speed due to its fast hold time constraints. However, they present no advantage against single edge flip flops.