DocumentCode :
2394251
Title :
New technologies in isolation and capacitor process for sub 0.1μm DRAM
Author :
Chung, U-In ; Yoo, Cha-Young ; Hong, Soo-Jin
Author_Institution :
Process Dev., Samsung Electron. Co., Kyungki, South Korea
fYear :
2003
fDate :
6-8 Oct. 2003
Firstpage :
17
Lastpage :
20
Abstract :
New technologies for sub 0.1 μm DRAM devices are reviewed and discussed in views of shallow trench isolation and capacitor process. In order to enhance the gap filling and reduce the accumulated mechanical stress in STI, Polysilazane-SOG pillar is introduced at the trench bottom. Additionally, poly-Si filling process is also developed to minimize channel edge effect. HfO2 deposited by atomic layer deposition is employed to lower the Toxeq. down to about 25Å. Toxeq. can be reduced further by introduction of TiN metal electrode. TiN electrode capacitor of Toxeq. 15Å shows the stable leakage current. Ru electrode help Toxeq. scale down to 10Å. It is concluded that sub 0.1 μm devices can be manufacturable through the introduction of new technologies and materials.
Keywords :
DRAM chips; capacitors; dielectric devices; dielectric materials; dielectric thin films; elemental semiconductors; filled polymers; hafnium compounds; internal stresses; isolation technology; leakage currents; polymer films; ruthenium; silicon; titanium compounds; 0.1 micron; 10 Å; 15 Å; 25 Å; DRAM; HfO2; Ru; Ru electrode; STI; Si; TiN; TiN electrode capacitor; atomic layer deposition; channel edge effect; gap filling; leakage current; mechanical stress; polysilazane-SOG pillar; shallow trench isolation; trench bottom; Atomic layer deposition; Capacitors; Electrodes; Filling; Hafnium oxide; Isolation technology; Leakage current; Random access memory; Stress; Tin;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, Systems, and Applications, 2003 International Symposium on
ISSN :
1524-766X
Print_ISBN :
0-7803-7765-6
Type :
conf
DOI :
10.1109/VTSA.2003.1252540
Filename :
1252540
Link To Document :
بازگشت