Title :
A 1.2V low leakage low cost 90 nm CMOS wireless technology with a 60 nm transistor gate length
Author :
Yang, S. ; Pollack, G. ; Wang, X. ; Potla, S. ; Baldwin, G. ; Chen, F. ; Mehrad, F. ; Tran, Thomas ; Sadra, K. ; Chidambaram, P.R. ; Chakravarthi, S. ; Bowen, C. ; Wells, G. ; Olsen, L. ; Wu, J. ; Houston, T. ; Machala, C. ; Johnson, S.
Author_Institution :
Texas Instrum., Dallas, TX, USA
Abstract :
In this paper, we have demonstrated a low-leakage low-cost 90 nm technology with a 60 nm gate length for high performance operation by using 193 nm strong-phase-shift lithography, nitrided gate oxide, aggressively scaled MDD junctions and 6-level Cu/low-k interconnects.
Keywords :
CMOS integrated circuits; bipolar transistors; copper; dielectric materials; integrated circuit interconnections; lithography; 1.2 V; 193 nm; 60 nm; 90 nm; CMOS wireless technology; Cu; interconnects; nitrided gate oxide; phase-shift lithography; transistor gate length; CMOS process; CMOS technology; Copper; Costs; Diodes; Implants; Instruments; MOS devices; MOSFETs; Metals industry;
Conference_Titel :
VLSI Technology, Systems, and Applications, 2003 International Symposium on
Print_ISBN :
0-7803-7765-6
DOI :
10.1109/VTSA.2003.1252562
