An effective physical synthesis technique for multiplier

Author

Wang, Cheng-Yeh ; Yang, Ya-Chi ; Jou, Jing-Yang

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2003

fDate

6-8 Oct. 2003

Firstpage

192

Lastpage

195

Abstract

This paper presents an effective multiplier synthesis algorithm for cell-based multipliers. By using a novel tree generation algorithm with timing consideration for each vertical compressor slice(VCS), our synthesizer generates multipliers automatically with very promising results.

Keywords

CMOS logic circuits; adders; digital arithmetic; integrated circuit modelling; multiplying circuits; cell based multipliers; multiplier synthesis algorithm; novel tree generation algorithm; physical synthesis technique; vertical compressor slice; Arithmetic; Delay effects; Digital signal processing; Heart; Joining processes; Production; Synthesizers; Timing; Tree data structures; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 2003 International Symposium on

ISSN

1524-766X

Print_ISBN

0-7803-7765-6

Type

conf

DOI

10.1109/VTSA.2003.1252585

Filename

1252585

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2395073