Title :
A testable BIST design for PLL
Author :
Chang, Yeong-Jar ; Lin, Shen-Tien ; Luo, Kun-Lun ; Wu, Wen-Ching
Author_Institution :
SoC Technol. Center, Ind. Technol. Res. Inst., Hsinchu, Taiwan
Abstract :
We present a testable built-in self test(BIST) design for phase-lock loop(PLL). The design can measure the clock jitter for PLL with high precision and high accuracy due to better utilization of the test integration and test subtraction techniques. Although the BIST circuit is implemented by all digital standard cells to achieve better reliability, it can even be applied to measure the analog clock jitter. Besides, for some DfT (design for test) techniques inserted to make BIST itself testable, we discuss the trade-off among area, timing, number of test patterns and fault coverage in this paper.
Keywords :
built-in self test; cellular arrays; design for testability; integrated circuit testing; phase locked loops; timing jitter; BIST circuit; DFT; PLL; analog clock jitter; built-in self test design; design for testability; digital standard cells; fault coverage; phase lock loop; testable BIST design; timing jitter; Automatic testing; Built-in self-test; Circuit testing; Clocks; Integrated circuit measurements; Integrated circuit reliability; Jitter; Measurement standards; Phase locked loops; Subtraction techniques;
Conference_Titel :
VLSI Technology, Systems, and Applications, 2003 International Symposium on
Print_ISBN :
0-7803-7765-6
DOI :
10.1109/VTSA.2003.1252588
