Title :
Layout design of high-quality SOI varactor
Author :
Chen, Han-Yu ; Chen, Kun-Ming ; Huang, Guo-Wei ; Huang, Chi-Huan ; Yang, Tsung-Hsi ; Chun-Yen Chang
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
This paper presents the geometry effect on the characteristics of accumulation type SOI varactor with mesa-isolation technology. Constant gate area varactors with various geometry condition were implemented to investigate the effects of layout design parameters on overall varactor performance. Physical and mathematic analysis based on the measurement results show that parasitic capacitance at the edge of active region seriously degrades the device quality factor at smallest gate length. The optimized SOI varactor has a quality factor Q of about 150/GHz/pF at medium gate length varactor. The experiment result can serve as a design reference for high-quality SOI varactors.
Keywords :
MOS capacitors; Q-factor; elemental semiconductors; isolation technology; silicon; silicon-on-insulator; varactors; SOI varactor layout design; Si; device quality factor; geometry effect; mathematic analysis; mesa isolation technology; parasitic capacitance; physical analysis; silicon on insulator; CMOS technology; Capacitance measurement; Geometry; Materials science and technology; Parasitic capacitance; Q factor; Radio frequency; Silicon on insulator technology; Substrates; Varactors;
Conference_Titel :
VLSI Technology, Systems, and Applications, 2003 International Symposium on
Print_ISBN :
0-7803-7765-6
DOI :
10.1109/VTSA.2003.1252606
