Title :
Ultra-Low-Power Cascaded CMOS LNA With Positive Feedback and Bias Optimization
Author :
Mu-Tsung Lai ; Hen-Wai Tsao
Author_Institution :
Dept. of Electr. Eng., Nation Taiwan Univ., Taipei, Taiwan
Abstract :
A novel circuit topology for a CMOS low-noise amplifier (LNA) is presented in this paper. By employing a positive feedback technique at the common-source transistor of the cascade stage, the voltage gain can be enhanced. In addition, with the MOS transistors biased in the moderate inversion region, the proposed LNA circuit is well suited to operate at reduced power consumption and supply voltage conditions. Utilizing a standard 0.18-μm CMOS process, the CMOS LNA has been demonstrated for 5-GHz frequency band applications. Operated at a supply voltage of 0.6 V, the LNA with the gain-boosting technique achieves a gain of 13.92 dB and a noise figure of 3.32 dB while consuming a dc power of 834 μW. The measured P1-dB and input third-order intercept point are -22.2 and -11.5 dBm, respectively
Keywords :
CMOS analogue integrated circuits; MOSFET; cascade networks; circuit feedback; low noise amplifiers; low-power electronics; network topology; transistor circuits; CMOS low-noise amplifier; CMOS process; LNA circuit; MOS transistor; bias optimization; cascade stage; circuit topology; common-source transistor; frequency 5 GHz; frequency band application; gain 13.92 dB; gain-boosting technique; input third-order intercept point; inversion region; noise figure 3.32 dB; positive feedback; power 834 muW; power consumption; size 0.18 mum; supply voltage; ultra-low-power cascaded CMOS LNA; voltage 0.6 V; voltage gain; CMOS; gain boosting; low-noise amplifier (LNA); moderate inversion; positive feedback; ultra-low power; ultra-low voltage;
Journal_Title :
Microwave Theory and Techniques, IEEE Transactions on
DOI :
10.1109/TMTT.2013.2256144