Design methodology for high performance heterogeneous SoC´s for converged metropolitan area networks

Author

Gopi, Paramesh ; Chao, Emil ; Li, G.P.

Author_Institution

Marvell Semicond. Inc., Irvine, CA, USA

fYear

2003

fDate

2003

Firstpage

300

Lastpage

303

Abstract

We present a top-down design methodology for scalable multi-gigabit per second packet networking silicon in standard CMOS processes. The theory is used to drive the design of a 2.5-10 Gbps packet forwarding SoC with deterministic latency for high performance voice gateways.

Keywords

CMOS logic circuits; elemental semiconductors; high-speed integrated circuits; integrated circuit interconnections; internetworking; metropolitan area networks; network routing; silicon; system-on-chip; 2.5 to 10 Gbit/s; CMOS process; Si; converged metropolitan area networks; high performance heterogeneous SoC; high performance voice gateways; multigigabit per second packet networking silicon; top-down design method; CMOS process; Design methodology; Integrated circuit interconnections; Logic arrays; Metropolitan area networks; Packet switching; Silicon; Switches; Telecommunication switching; Time division multiplexing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 2003 International Symposium on

ISSN

1524-766X

Print_ISBN

0-7803-7765-6

Type

conf

DOI

10.1109/VTSA.2003.1252613

Filename

1252613

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2395523