DocumentCode
2395545
Title
VLSI architecture design of modified Euclidean algorithm for Reed-Solomon code
Author
Chang, Y.-W. ; Jeng, J.H. ; Truong, T.K.
Author_Institution
Coll. of Electr. & Inf. Eng., I-Shou Univ. Kaohsiung, Kaohsiung County, Taiwan
fYear
2003
fDate
2003
Firstpage
304
Lastpage
306
Abstract
In this paper, a novel-decoding algorithm based on Euclidean method is developed correct errors for RS codes. This new decoding algorithm can solve the Berlekamp´s key equation to find the error locator and evaluator polynomials simultaneously without performing the computation of polynomial division and finite field element inversion. Moreover, the number of iterations is fixed, which equals the minimum distance minus one. Also, it saves many extra controlling circuits. Therefore this novel-decoding algorithm is regular, efficient, simple and easy to implement.
Keywords
Reed-Solomon codes; VLSI; iterative decoding; polynomials; Berlekamp equation; Euclidean algorithm; RS codes; Reed-Solomon code; VLSI architecture design; decoding algorithm; error evaluator polynomials; error locator polynomials; finite field element inversion; Algorithm design and analysis; Computer architecture; Equations; Error correction codes; Galois fields; Iterative decoding; Performance evaluation; Polynomials; Reed-Solomon codes; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications, 2003 International Symposium on
ISSN
1524-766X
Print_ISBN
0-7803-7765-6
Type
conf
DOI
10.1109/VTSA.2003.1252614
Filename
1252614
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