SoC Design Quality, Cycletime, and Yield Improvement Through DfM

Technology, CAD, and design are increasingly more challenged by design-for-manufacturability rules and guidelines required to improve pattern transfer quality to the reticle and silicon wafer. One key reason for this challenge is the variability of the layout, which for SoC designs beyond the 100 nm technology node should no longer be subject only to short range design rule checks concerning individual layout features. To include the impact of medium and long-range pattern interactions (across-die or exposure field) into the design process, one should change layout architecture methodology distributed so far among technology, CAD, and design groups and using manual drawing techniques or semi-automated tools with different quality standards. This task becomes even more important for the SoC layout for analog/RF applications where signal propagation is sensitive to device matching requirements and capacitive coupling. At that point, IC designer had two options to control the layout freedom: by enforcing new, more restrictive design rules or by using parameterized layout based on standard cells proven on silicon, including all electrically extracted RET, OPC, and dummy features. In this work, it was shown that the standardized layout is the preferred option leading to the improved quality, reduced cycletime, and higher yields