DocumentCode
2395904
Title
Execution of algorithms using a Dynamic Dataflow Model for Reconfigurable Hardware - A purpose for Matching Data
Author
Silva, Jorge Luiz E
Author_Institution
Dept. of Comput. Sci., Sao Paulo Univ., Sao Carlos
fYear
2006
fDate
Dec. 2006
Firstpage
115
Lastpage
119
Abstract
The dynamic dataflow model in a reconfigurable hardware is a project of an architecture that explores the parallelism in a natural form, using the characteristics of the partial reconfigurable hardware. This project has been developed, and there are results of proof-of-concepts for a protocol between the operators. Specifically on this part of the project is the purpose to matching data into the operators. This paper describes the structure for the matching data
Keywords
field programmable gate arrays; protocols; dynamic dataflow model; matching data structure; operator protocol; reconfigurable hardware; run-time reconfiguration; Application software; Computer science; Data structures; Fires; Hardware; Heuristic algorithms; Protocols; Real time systems; Runtime; System-on-a-chip; Dataflow Architecture; Matching Data Structure; Reconfigurable Hardware; Run-time Reconfiguration; Tagged-token;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip for Real-Time Applications, The 6th International Workshop on
Conference_Location
Cairo
Print_ISBN
1-4244-0898-9
Type
conf
DOI
10.1109/IWSOC.2006.348219
Filename
4155272
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