Embedding and Verification of PSL using ASM

This paper proposes a methodology to integrate the property specification language (PSL) in the verification process of systems designed using abstract states machines (ASMs). A specification of PSL in ASM was provided, which allows us to integrate PSL properties as part of the design. For the verification, a technique based on the AsmL tool was proposed that translates the ASM code (containing both the design and the properties) into a finite state machine (FSM) representation. The generated FSM was used to run model checking on an external tool, here SMV. The approach takes advantage from the ASM language capabilities to model designs at the system level as well as from the power of the AsmL tool in generating both a C# code and an FSM representation from an ASM model. The approach was applied on SystemC designs, which are translated into ASM models. Experimental results on a bus structure from the SystemC library showed a superiority of the approach to conventional verification