A Novel Scheduling methodology for ASIC Design

This paper presents a new VHDL intermediate format CDFG (control data flow graph) and a minimal hardware resource scheduling algorithm for ASIC design automation. The intermediate format, CDFG represents the constraints which limit hardware design such as conditional branch, sequential operation and time constraints. The proposed scheduling algorithm could handle the conditional branches effectively and could check the timing constraints efficiently. It minimizes the total operating time by reducing the number of the constraints as maximal as possible, determining the number of control steps in minimum bound. The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples