Parallel error-correction architecture

Parallel error-correction permits maximum throughput to be obtained from state-of-the-art RISC and CISC pipelined microprocessors used in high-performance digital avionics applications. As clock rates grow for commercially-based technology, it becomes increasingly prohibitive to permit memory bandwidth to be restricted by traditional in-line error correction methods. An alternative architecture is presented utilizing off-line error detection and correction, that clears errors essentially “after-the-fact” (or as needed); allowing a direct flow path from memory to central processor unit