An FPGA Implementation of a Hopfield Optimized Block Truncation Coding

Author

Saif, Sherif ; Abbas, Hazem M. ; Nassar, S.M. ; Wahdan, A.A.

Author_Institution

Mentor Graphics Corp., Cairo

fYear

2006

fDate

Dec. 2006

Firstpage

169

Lastpage

172

Abstract

This paper presents an implementation for image compression using variable block truncation coding (BTC) on a field programmable gate array (FPGA). The compression technique is improved by employing a cost function obtained using Hopfield neural network (HNN), upon which a block is classified as either a high- or a low-detail block. Accordingly, different blocks are coded with different bit rates and thus better compression ratios are achieved. The paper formulates the utilization of HNN within the BTC algorithm in such a way that a viable FPGA implementation is produced. The Xilinx Virtex EBTC implementation has shown to provide a processing speed of about 1.113 times 10⁶ of pixels per second with a compression ratio which varies between 1.25 and 2 bits per pixel, according to the image homogeneity

Keywords

Hopfield neural nets; field programmable gate arrays; image coding; FPGA implementation; Hopfield neural network; Xilinx Virtex; field programmable gate array; image compression; variable block truncation coding; Application software; Costs; Field programmable gate arrays; Hardware; Hopfield neural networks; Image coding; Network synthesis; Pixel; Real time systems; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip for Real-Time Applications, The 6th International Workshop on

Conference_Location

Cairo

Print_ISBN

1-4244-0898-9

Type

conf

DOI

10.1109/IWSOC.2006.348230

Filename

4155283