The ASIC and FPGA design challenge

Our ability to integrate increasingly large scale systems on silicon is determined and constrained not only by manufacturing technology but also by the underlying complexity of the system architectures. These architectures, usually thought of in terms of different interconnected software and hardware functions, rarely result in global regularity in terms of data and control flow or in extensive structural regularity at the circuit level. This `disorder´ in the system architecture results in the need to provide and support a sophisticated design process that leads a designer safely through the necessary stages. Complex suites of computer aided engineering tools have been developed to help maintain consistency between the many representations of the design while assisting with the generation and verification of major building blocks. The task of the ASIC or FPGA designer is to create a physical entity that performs a specified function with a specified behavioural response to given data and control signals. As overall constraints, the system specification will include physical size and power dissipation limits and maximum costs. Furthermore, a time scale for successful completion of the design and target dates for production will form part of the `contract´. To be successful, the design team must maintain many views concurrently and be able to cross-verify these representations at a number of levels of abstraction. In broad terms, these views comprise the following items: system level; processor architecture; machine structures; and implementation