Host interface design for experimental, very high-speed networks

A critical bottleneck in very high-speed networks is the interface between host computers and the network. Some of the fundamental problems of designing such an interface to make full use of the available network bandwidth are examined. These problems are those which are independent of the nature of the underlying network and those which depend on the network. The most notable problem is the limitations of current bus bandwidths. An architecture is proposed to minimize the effects of this limitation and with the aim of providing higher speeds as bus bandwidths increase. The proposed interface consists of a network-independent part, which performs transport-level functions, and a network-dependent part, which deals with the units of multiplexing that are handled by the network. Although it is believed that the former can be (mostly) implemented by an off-the-shelf processor, the latter is likely to require a substantial amount of dedicated hardware. The requirements for this hardware and possible implementation are described.<>