Test vehicle for a wafer-scale field programmable gate array

Author

Dufort, B. ; Chapman, G.H.

Author_Institution

Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada

fYear

1995

fDate

18-20 Jan 1995

Firstpage

33

Lastpage

42

Abstract

A test vehicle for a wafer scale FPGA has been developed. A symmetrical RAM-programmable FPGA, lookup table based logic block and segmented channel routing are used. In this paper, we emphasize on the practical problems inherent to wafer scale FPGAs: redundancy, power shorts, clock distribution, cell and bus testing. The laser-link process is used to interconnect working cells and form a defect free array of FPGA cells. The defect avoidance algorithm is designed to minimize the delay between working cells, an important parameter for FPGA users

Keywords

CMOS logic circuits; delays; field programmable gate arrays; integrated circuit layout; integrated circuit testing; logic design; logic testing; network routing; redundancy; wafer-scale integration; WSI; bus testing; cell testing; clock distribution; defect avoidance algorithm; defect free array; delay minimisation; field programmable gate array; laser-link process; lookup table based logic block; power shorts; redundancy; segmented channel routing; symmetrical RAM-programmable FPGA; test vehicle; wafer scale FPGA; Algorithm design and analysis; Clocks; Delay; Field programmable gate arrays; Optical arrays; Programmable logic arrays; Routing; Table lookup; Testing; Vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

Wafer Scale Integration, 1995. Proceedings., Seventh Annual IEEE International Conference on

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-2467-6

Type

conf

DOI

10.1109/ICWSI.1995.515436

Filename

515436