• DocumentCode
    2397151
  • Title

    A RAM-based neural network architecture for wafer scale integration

  • Author

    Bolouri, Hamid ; Morgan, Paul ; Peacock, Chris

  • Author_Institution
    Eng. Res. & Dev. Centre, Hertfordshire Univ., Hatfield, UK
  • fYear
    1995
  • fDate
    18-20 Jan 1995
  • Firstpage
    82
  • Lastpage
    90
  • Abstract
    The paper presents the design of a RAM-based Artificial Neural Network (ANN) architecture which is particularly well suited to WSI implementation. Using data from a VLSI test chip and prototype system manufactured in 1993, we compare the performance and complexity of FPGA, VLSI and WSI RAM-based neural systems
  • Keywords
    integrated memory circuits; neural chips; neural net architecture; random-access storage; wafer-scale integration; HyperNet; RAM; neural network architecture; wafer scale integration; Artificial neural networks; Hardware; Manufacturing; Neural networks; Neurons; Prototypes; Random access memory; Read-write memory; Very large scale integration; Wafer scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Wafer Scale Integration, 1995. Proceedings., Seventh Annual IEEE International Conference on
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    0-7803-2467-6
  • Type

    conf

  • DOI
    10.1109/ICWSI.1995.515441
  • Filename
    515441
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2397151