Silicon hybrid wafer scale integration (SHWSI)-a discrete integrated circuit (IC) interconnect scheme

Author

Kolesar, Edward S. ; Takahashi, Grant L. ; Reamy, Philip C.

Author_Institution

Dept. of Eng., Texas Christian Univ., Fort Worth, TX, USA

fYear

1995

fDate

18-20 Jan 1995

Firstpage

122

Abstract

Summary form only given. A silicon-hybrid wafer-scale integration (SHWSI) fabrication technology has been developed to interconnect discrete integrated circuit (IC) die. As a demonstration of this technology, a simple, 3-bit, asynchronous binary counter circuit was implemented using two discrete complementary metal-oxide semiconductor (CMOS) IC die that were independently fabricated by the Metal-Oxide-Semiconductor Implementation System (MOSIS) foundry. When compared to a complementary wire-bonded interconnect scheme, the SHWSI technology was found to manifest superior electrical performance at operating (clock) frequencies as high as 40 MHz

Keywords

CMOS logic circuits; asynchronous circuits; counting circuits; hybrid integrated circuits; integrated circuit interconnections; silicon; wafer-scale integration; 3 bit; 40 MHz; CMOS IC die; MOSIS foundry; SHWSI fabrication technology; Si; asynchronous binary counter circuit; discrete integrated circuit interconnect; silicon hybrid wafer scale integration; CMOS integrated circuits; CMOS technology; Counting circuits; Fabrication; Foundries; Integrated circuit interconnections; Integrated circuit technology; MOS devices; Silicon; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Wafer Scale Integration, 1995. Proceedings., Seventh Annual IEEE International Conference on

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-2467-6

Type

conf

DOI

10.1109/ICWSI.1995.515445

Filename

515445