An experimental fault-tolerant active substrate MPC MCM using standard gate array technology

The Massively Parallel Computing (MPC) arena continues to demand ever more powerful and compact building-blocks, especially for the construction of embedded-MPC systems. Multi-Chip Modules (MCMs) offer a means of implementing such building-blocks, but have been shown to suffer from cost and delivery problems at the complexity levels required. As these problems stem from infant die mortality, assembly yield losses and the `known-good-die´ problem it has been proposed to incorporate fault-tolerance into an MCM to permit these faults to be overcome by programmable MCM configuration, rather than costly and time-consuming module re-work. Theoretical studies have confirmed the potential of this approach, but it remains to evaluate practical means of its implementation. The present paper reports the results of an initial practical experiment into the design of such an MPC MCM that uses a fault-tolerant active substrate based on an existing gate-array wafer