A cache coherency protocol for multiprocessor chip

In this paper, we propose a snoop cache protocol for the WSI implementation which minimizes the accesses to the shared memory. In the modified-Keio protocol, both write-invalidate and write-update type protocols can be used according to the nature of the shared data. It also supports the simple synchronization mechanism with Fetch&Dec operation and inter-processor interrupt. Detailed simulation with practical parallel applications shows the efficiency of our protocol. Now we are constructing a prototype machine using R3000 processors to evaluate the actual performance of the protocol