The influence of process parameter variations on the signal distribution behaviour of wafer scale integration devices

One of the key issues of the implementation of circuits using wafer scale integration technologies is the synchronous distribution of signals, either clock, data or control over a large area of silicon. Fluctuations of process parameters can have a major influence on the performance of these devices. Within this paper, simulations, based on real measured process parameters, are undertaken to show the sensitivity of different signal distribution strategies to these variations