Reconfiguration and routing in defective WSI processor arrays

In this paper we discuss an alternative to the traditional approach of reconfiguration and adaptive routing. We first reconfigure a faulty processor array, not with the goal of producing a regular topology, but rather to increase the bandwidth of the network (increase the conductivity of a networks defined by percolation theory). This reconfiguration will provide us with a network which is disordered and irregular but has sufficient connectivity to allow the implementation of message passing techniques (such as store and forward or wormhole techniques). In the second part of our techniques we implement modified adaptive routing algorithms which can provide deadlock free, livelock free and starvation free routing between most elements in the reconfigured array. In the final part of our approach, we utilize a topology mapping to map the physical addresses of processor elements to logical coordinates, and an inverse mapping to map logical coordinates to physical addresses. This allows regular and irregular topologies to be implemented on the processor array, and provide reliable and effective communication between required processing elements