DocumentCode :
2397671
Title :
An easily-testable cube-connected cycles structure
Author :
Choi, Yoon-Hwa ; Choi, Ja-Young ; Kim, Yu-Seok
Author_Institution :
Dept. of Comput. Eng., Hong Ik Univ., Seoul, South Korea
fYear :
1995
fDate :
18-20 Jan 1995
Firstpage :
349
Lastpage :
358
Abstract :
In this paper, we present an easily-testable cube-connected cycles (CCC) structure for VLSI/WSI implementation. The concept of boundary scan is used to provide test vectors and capture the resulting responses. A simple design modification is made to considerably reduce the test application time. The test access port of each processing element (PE) is utilized to perform comparisons between PEs. Single-bit comparators are appropriately placed in order to locate faults in the PEs and interconnection links in the CCC structure. The scheme is shown to be simple enough to be practically useful
Keywords :
VLSI; boundary scan testing; design for testability; fault location; hypercube networks; integrated circuit testing; logic testing; wafer-scale integration; VLSI; WSI implementation; boundary scan; cube-connected cycles structure; design modification; easily-testable structure; fault location; single-bit comparators; test access port; test application time reduction; test vectors; Application software; Circuit faults; Circuit testing; Flip-flops; Hypercubes; Integrated circuit interconnections; Parallel processing; Performance evaluation; Printed circuits; Topology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Wafer Scale Integration, 1995. Proceedings., Seventh Annual IEEE International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-2467-6
Type :
conf
DOI :
10.1109/ICWSI.1995.515469
Filename :
515469
Link To Document :
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