A 40 MHz IF fourth-order double-sampled SC bandpass ΣΔ modulator

Author

Bazarjani, Seyfi ; Snelgrove, Martin

Author_Institution

Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada

Volume

1

fYear

1997

fDate

9-12 Jun 1997

Firstpage

73

Abstract

A fully differential double-sampled SC architecture for a fourth-order bandpass ΣΔ modulator is presented. This architecture is based on a double-sampled SC delay circuit. The effect of opamp DC gain on the notch frequency of this modulator is analyzed. The modulator is implemented in a 0.5 μm CMOS technology and operates at a clock frequency of 80 MHz. Thus, the effective sampling rate is 160 MHz. The image signal is about 40 dB below the fundamental signal. Over a 2 MHz bandwidth centered at 40 MHz, the measured SNDR is 45 dB (not including the image). The circuit operates at 3.3 V and consumes 65 mW

Keywords

CMOS integrated circuits; delay circuits; modulators; sigma-delta modulation; signal sampling; switched capacitor networks; 0.5 micron; 2 MHz; 3.3 V; 40 to 160 MHz; 45 dB; 65 mW; CMOS technology; IF fourth-order ΣΔ modulator; SC delay circuit; bandpass ΣΔ modulator; bandpass sigma-delta modulator; double-sampled SC architecture; fully differential architecture; notch frequency; opamp DC gain; CMOS technology; Circuits; Clocks; Delay; Delta modulation; Frequency conversion; Image sampling; Sampling methods; Signal processing; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on

Print_ISBN

0-7803-3583-X

Type

conf

DOI

10.1109/ISCAS.1997.608536

Filename

608536