Title :
A 60 ?? 58 Integrated Multiplier
Author :
Helwig, Klaus ; Getzlaff, Klaus ; Trong, Son Dao
Abstract :
A dense 60 × 58 Multiplier will be described which is integrated on a chip containing a complete Coprocessor. The Multiplier has been fabricated in a triple-metal, single-polysilicon CMOS process with 1.0 um lithography and CMOS devices with 0.5 urn effective channel length. Circuit techniques are described that obtain a multiplier with high density (3.5mm × 5.7mm) and high speed. The typical delay is 18 ns.
Keywords :
CMOS logic circuits; coprocessors; multiplying circuits; photolithography; CMOS devices; circuit techniques; coprocessor; effective channel length; integrated multiplier; lithography; size 0.5 mum; size 1.0 mum; time 18 ns; triple-metal single-polysilicon CMOS process; Adders; Automatic logic units; CMOS process; Coprocessors; Delay; Lithography; Logic circuits; Multiplexing; Registers; Wiring;
Conference_Titel :
Solid-State Circuits Conference, 1989. ESSCIRC '89. Proceedings of the 15th European
Conference_Location :
Vienna
Print_ISBN :
3-85403-101-7
DOI :
10.1109/ESSCIRC.1989.5468056
