Silicon Clock Recovery IC´s for 2 to 3.5 Gbit/s

Author

Wang, Z. ; Langmann, U. ; Bosch, B.G.

Author_Institution

Inst. fur Elektron., Ruhr-Univ. Boehum, Bochum, Germany

fYear

1989

fDate

20-22 Sept. 1989

Firstpage

264

Lastpage

267

Abstract

A novel clock recovery IC for Gbit/s optical communication is presented, employing a 1:2 dynamic frequency divider scheme with an external resonator filter. It is based on a conventional Si bipolar process. Two versions of the same IC design are presented, one optimized for 2 to 3 Gbit/s, the other for 3 to 4 Gbit/s. Clock recovery is demonstrated at 2.23 and 3.52 Gbit/s, leading to clock signals of 1.115 and 1.76 GHz, respectively. Measured rms clock phase jitter is less than 0.3°.

Keywords

digital integrated circuits; elemental semiconductors; frequency dividers; integrated circuit design; integrated optoelectronics; jitter; optical communication; optical filters; resonator filters; silicon; synchronisation; IC design; RMS clock phase jitter; Si; bipolar process; bit rate 2 Gbit/s to 3.5 Gbit/s; bit rate 3 Gbit/s to 4 Gbit/s; dynamic frequency divider scheme; frequency 1.115 GHz; frequency 1.76 GHz; optical communication; resonator filter; silicon clock recovery IC; Clocks; Design optimization; Frequency conversion; Jitter; Optical fiber communication; Optical frequency conversion; Phase measurement; Photonic integrated circuits; Resonator filters; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1989. ESSCIRC '89. Proceedings of the 15th European

Conference_Location

Vienna

Print_ISBN

3-85403-101-7

Type

conf

DOI

10.1109/ESSCIRC.1989.5468062

Filename

5468062