Thermomechanical Characteristics of Copper Through-Silicon via Structures

The 3-D integrated circuit technologies with through-silicon via (TSV) structure have been attracting increasing attentions due to enhanced microchip function and performance. However, the high residual stress in the TSV structure caused by a mismatch of thermal expansion between copper and its surrounding substrate is a potential risk for the reliability of the chip performance. In this paper, the characteristics of thermomechanical behavior in a wafer with copper TSVs were studied using electron backscattered diffraction (EBSD) and finite-element modeling. The high-resolution strain distribution maps were obtained using EBSD-based kernel average misorientation method. The results provided direct observation of the local strain in copper TSV, and the microstructural characteristics of copper TSV were also investigated. Finite-element analysis was performed to determine the stress distributions and to account for the strain in TSV observed through EBSD and scanning electron microscopy.