The system for delay measurement in ethernet networks on NetFPGA cards

Author

Michalski, Marek

Author_Institution

Dept. of Commun. & Comput. Networks, Poznan Univ. of Technol., Poznan, Poland

fYear

2014

fDate

1-4 July 2014

Firstpage

114

Lastpage

119

Abstract

In this paper the system for measuring delay in computer networks is presented. This system has several blocks, the main of which is the NetFPGA card with appropriate software running in its hardware chip programmed in HDL - Verilog. The others blocks are implemented in typical software (C, C++, C#), they realize the functionality of the management and the graphical user interface. The presented system makes it possible to measure the delay in switched and routed Ethernet networks in many different configurations. One of the most valuable features of this system is its cost, the second one is the resolution of the measured time periods. This system was developed for the NetFPGA cards with four 1Gbps ports, it has been also successfully implemented in NetFPGA cards with 10G interfaces. Both version have been compared with high class industrial network analyzers.

Keywords

computer software; delay systems; field programmable gate arrays; graphical user interfaces; local area networks; time measurement; HDL-Verilog; computer networks; delay measurement system; graphical user interface; hardware chip programmed; industrial network analyzers; management functionality; netFPGA cards; routed Ethernet networks; software running; time period resolution measurement; Delays; Hardware; Laboratories; Ports (Computers); Software; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

High Performance Switching and Routing (HPSR), 2014 IEEE 15th International Conference on

Conference_Location

Vancouver, BC

Type

conf

DOI

10.1109/HPSR.2014.6900890

Filename

6900890